In order to minimize the switching delay of a transistor, subject to other constraints such as power consumption, it is critical to minimize the degree of misalignment between the transistor's source/drain region(s) and the channel(s) to which they are connected. Along the axis perpendicular to the boundary between a source/drain and a channel (the “length axis”), if a source region is separated from the channel by an excessive distance (typically up to approximately 10 nm in silicon-based high-speed technology), the resistance between the source region and the channel limits the current carrying capacity of the transistor for typical “on-state” terminal biases. On the other hand, if the separation is reduced such that the source region overlaps the gate associated with the channel, then for excessive source-to-gate overlap the capacitance between the source and the gate will limit the speed at which circuits using the transistor can be operated.
Along the direction parallel to the boundary between the source and the channel (the “width axis”), if the edge of the channel extends beyond the edge of the source region, such that some of the channel edge is not contacted by the source, then the resistance between the source and the channel is increased relative to the case in which the source is aligned with the edge of the channel. On the other hand, if the edge of the source extends beyond the edge of the channel, such that not all of the source edge is in contact with channel, then the capacitance associated with the source is increased relative to the case in which the source edge is aligned with the channel edge. This case also results in reduced switching speeds relative to the case of a well-aligned edge. Thus, proper alignment along both the width and length axes is critical to optimizing the design of transistors, and in particular metal oxide semiconductor field-effect transistors (MOSFETs).
Alignment between regions in a semiconductor process can generally be achieved in two ways. One is for the layers of materials that will eventually make up the device to be independently patterned, aligned either manually or via automated alignment systems. For example, a first region of the device can be patterned, yielding “alignment marks” which can then be used in subsequent patterning processes as a reference. That is, a mask used to pattern a subsequent region of the device can be oriented relative to the alignment mark(s) left by the first patterning operation such that, within tolerances characteristic of the alignment and patterning process being used, the local degrees of freedom (for example, in-plane length-axis position, in-plane width-axis position, rotation, length-axis scale factor, width-axis scale factor, and shear) between the two patterns is constrained. The key is that each of these degrees of freedom is constrained only to within tolerances associated with the alignment and pattern transfer processes; so, as the characteristic dimensions of transistors is reduced over time, these tolerances must meet an increasingly restrictive standard. Other alignment strategies involve aligning each of two layers to alignment marks formed from an earlier patterning step; however, in each case the alignment tolerances remain a limiting factor.
A preferable approach is a “self-aligned” process wherein the relative orientation and/or position of two or more regions or boundaries is constrained as a natural consequence of the fabrication process, and not the explicit positioning or orienting of masks or other pattern transfer mechanisms. This eliminates the variation associated with the alignment of masks. Instead, on-wafer features or chemistry, for example, are used to constrain the formation of or the character of material in regions of the device under fabrication. Several self-aligned processes presently exist in the art:
A. Self-Alignment via Ion Implantation
Today, MOSFETs are often fabricated using impurities of silicon, for example Ar (for n-type) and/or B (for p-type), to form conducting source/drain regions. Typically the gate is patterned on a gate insulator in the channel region(s), with a thick “field oxide” in “field” region(s). In source and drain region(s), the silicon is capped only with a thin layer of SiO2, for example. Then, an energetic beam of ions of the desired impurity is directed, typically within approximately 30 degrees of perpendicular, onto the wafer surface.
Where the ion beam impacts the gate material (possibly in combination with additional layers self-aligned thereto), the impurities are essentially blocked from penetrating into the silicon in the channel region(s). Likewise, in the field region(s) the thick field oxide blocks the impurities from entering any underlying silicon. In the source/drain region(s), however, the impurities penetrate the thin SiO2 layer and penetrate the underlying silicon. Following a suitable anneal to increase the fraction of substitutional, electrically active impurities, the source and drain region(s) are then made to be conducting. As the implant is naturally blocked from creating impurities in the silicon of the field and the channel region(s), the process is self-aligned.
There are alternate methods of introducing impurities into the silicon besides ion implantation. For example, a material containing a high concentration of the desired impurity can be deposited on the wafer surface. Where the silicon is exposed, or protected only with suitably thin and/or permeable materials, an appropriate thermal cycle can be employed to diffuse the impurity from the deposited layer into the silicon. The impurity-rich material can then be selectively removed from the surface, leaving impurity-rich silicon in the source/drain regions. Note, this approach does not generally constitute a “deposited source/drain” as that term is used in the context of the present invention described below, because, for example, the impurities are intentionally removed from the deposited material, displaced into the source/drain material (e.g., by diffusion facilitated by an anneal at elevated temperature), and the remaining deposited material subsequently removed. Thus, the deposited material is not itself the source/drain of the device.
Whether created by ion implantation or otherwise, however, a limitation of impurity-rich semiconductors, for example doped silicon, is that such devices exhibit low conductivity relative to metals. Stated differently, metals offer the promise of lower resistance source/drains. Additionally, with many semiconductors other than silicon, lower concentrations of “electrically active” impurities (substitutional impurities that contribute to the concentration of mobile electrons or holes) than those available with silicon are achievable. An example is n-type Ge. Further, the interface between impurity-rich and impurity-poor semiconductor is difficult to control to atom resolution, whereas metal/semiconductor interfaces are essentially atomically abrupt. Lack of abruptness and control each limit the precision with which the alignment between the source/drain and the gate and/or channel can be obtained. Further, these failings can contribute to “short channel” effects that degrade the control of the channel conductivity by the gate.
B. Self-Alignment via Chemical Reaction
Another approach to self-alignment is via a chemical reaction with exposed material. For example, assume an exposed silicon surface remains in the source/drain region, but the field region is protected by thick oxide, and the gate is completely protected by reaction-resistant layers, such as SiO2 and/or Si3N4. If a metal that reacts with Si, for example Pt, is then deposited on the exposed silicon surfaces, and the wafer is heated to a temperature sufficient to cause a reaction with that silicon, the reaction product can be formed only in the source/drain regions. Removal of the unreacted metal leaves a conductor (for example, PtSi) only in the source/drain regions, self-aligned along both the length axis (to the edge of the gate) and along the width axis (to the edge of the field oxide).
Although in the above example the metal is deposited, this approach does not generally constitute a “deposited source/drain” as that term is used in the context of the present invention. Instead, in this example the source/drain comprises the reacted material, not the reagent, and it is only reagents that are deposited. Stated differently, the source/drain is formed in the same material that forms the channel, not as the direct consequence of the deposition.
An issue with source/drain formation by chemical reaction is that it limits the range of materials that can be used for the source/drain conductor. Metal silicides, for example, result in a Schottky barrier to the silicon channel that limits the effective on-state conductance of the junction. An approach to reducing this resistance is to arrange for the silicidation reaction to consume sufficient silicon that the edge of the source(s) and possibly drain(s) extends under the gate. See, for example, U.S. Pat. No. 6,744,103 of Snyder, “Short-channel Schottky-Barrier MOSFET Device and Manufacturing Method”. As has been discussed above, however, this leads to increased gate-to-source, and possibly gate-to-drain, capacitance and also results in more severe “short-channel effects” than is the case for aligned source/drain—channel interfaces.
An approach to reduce these short-channel effects is disclosed in U.S. Pat. No. 6,509,609 of Zhang, et al., “Grooved Channel Schottky MOSFET”, wherein the gate is recessed in the semiconductor, yielding a U-shaped channel. Problems remain with this approach, however, including high gate-to-source and gate-to-drain capacitance, gate insulator integrity across the corner of the trench, increased local channel resistance due to a concave surface and the resulting electric field divergence from the gate, and high leakage current at negative gate-to-source biases. A preferred approach, as advanced by several of the present inventors in the above-cited co-pending U.S. patent application Ser. No. 10/217,758, is to reduce the height of the Schottky barrier between the channel and the source(s), for which the availability of a broader range of source/drain material options is advantageous.
C. Self-Alignment via Damascene Metal
An approach to using surface topography to form self-aligned metal layers is the “damascene process”, wherein metal is deposited in a recess and then “planarized”, for example via polishing, to remove excess material above the plane of the top of the recess. The result is metal remaining only in the recess. This technique has been used for the patterning of copper interconnects in SiO2, see, e.g., D. Edelstein et al., Full Copper Wiring in a Sub-0.25 μm CMOS ULSI Technology, Proceedings of the IEEE International Electron Device Meeting, pp. 773-776 (December 1997), and to form gate electrodes, see, e.g., A. Yagashita, et al., High performance damascene metal gate MOSFETs for 0.1 μm regime, IEEE Trans. Electron Devices, v.47 n.5, pp. 1028-1034 (2000).
FIGS. 1a-1f, reproduced from the Yagashita reference, illustrate the basics of the damascene process including the use of a “sacrificial gate”. As shown in FIG. 1a, a stack of a dummy gate oxide 10, a sacrificial polycrystalline Si gate 12, and a Si3N4 cap 14 is formed on a wafer 16 on which shallow trench isolation has been used to form the field oxide. The gate pattern is then transferred to the polycrystalline Si—Si3N4 stack using a photoresist mask 18. Referring to FIG. 1b, sidewall spacers 20 are then formed on the patterned gate stack and ion implantation then forms self-aligned source/drain regions 22/24. Referring to FIG. 1c, a thick SiO2 layer 26 is then deposited and planarized (e.g., by chemical mechanical polishing (CMP)) to the level of the Si3N4 cap 18 on the sacrificial gate. As shown in FIG. 1d, the Si3N4 cap 18, sacrificial gate 14, and the underlying “dummy” gate oxide 16 are then removed. Referring to FIG. 1e, a fresh gate insulator 28, for example SiO2 and/or a deposited metal oxide (e.g., TiN) 30, is then formed in the recess, followed immediately by the deposition of a metal gate (e.g., Al or W) 32. As shown in FIG. 1f, this gate metal 32 is subsequently planarized (e.g., via CMP) to the level of the previously planarized SiO2 layer 26, yielding a metal gate 34 self-aligned to the source/drain regions 22/24.
Another example, reported in U.S. Pat. No. 6,686,231, “Damascene Gate Process with Sacrificial Oxide in Semiconductor Devices”, discloses a damascene replacement gate process. In replacement gate processes, at least part of the recess for the damascene process results from removal of a sacrificial layer. Like the process described by Yagashita, however, this process does not provide for metal source/drain regions.
A process that provides metal source/drain contacts and a damascene-like metal gate is disclosed in U.S. Pat. No. 4,889,827, “Method for the Manufacture of a MESFET Comprising SelfAligned Gate”, and the results of that process are shown in FIG. 2 (which is adapted from the '827 patent). As shown, a first metal layer 36 is formed and capped with an insulator 38. A recess is patterned in these layers, sidewall spacers 40 and 42 are formed in therein, and then a second metal layer 44 for the gate is deposited between the spacers.
A primary disadvantage of this approach, were it to be applied to MOSFETs, is that the gate stack is processed subsequent to the source/drain. It is typical in the processing of MOSFETs that elevated temperatures are required to produce high-quality gate insulators. Consequently, the process sequence reported in the '827 patent would require that the source/drain stack be tolerant of the process conditions used for the gate stack, potentially a serious disadvantage. It is perhaps not surprising then that the '827 patent describes the damascene process only as it relates to MESFETs, wherein the “source”—the region which supplies carriers to the channel—is not the metal contact 36, but rather the doped region 46 in the vicinity of the channel region 48. In contrast, for a typical MOSFET, where the channel is formed in an inversion layer (or an accumulation layer in a region of otherwise insignificant concentration of carriers of the type in the channel), in the absence of a region doped with a high concentration of donors (n-channel FET) or acceptors (p-channel FET) to match the charge in the channel, a metal contact in the vicinity of the channel acts as a source directly.
Also, it is worth noting that the source/drain of the device shown in the '827 patent is not formed in a recess. As discussed above, the use of the recess allows the source/drain to be self-aligned relative to previously formed features. The '827 patent, on the other hand, describes the alignment features subsequent to the formation of the source/drains and fails to allow for width-axis alignment of the source/drain and the gate.
Finally, damascene contacts to sources/drains have been reported. For example, and with reference to FIGS. 3a and 3b, U.S. Pat. No. 4,713,356 of Hiruta, “Manufacturing MOS semiconductor device with planarized conductive layer”, describes how “source and drain regions” are “formed in a semiconductor substrate” using a gate layer as a mask. A conductive layer is then deposited and “etched back” to expose “the upper surface” of the gate electrode and the “top surface” of an insulating film (typically, the field oxide), yet leaving conducting material “on” the “source and drain regions”. This process, while it forms contacts to the source/drain regions via a deposition and damascene process, fails to form the actual source/drain in this fashion. Indeed, the '356 patent describes how “an n-type impurity is then ion-implanted in a substrate 50 using electrode 52 as a mask to form n+-type source and drain regions 54 and 56”.
Damascene contacts to a source/drain fundamentally differ from an actual damascene source/drain in several ways:                1. The implants forming source/drain regions 54 and 56 must be omitted if the conductors 58a and 58b are to function as the source/drain.        2. The spacer 60 must be severely limited in length to allow carriers to travel between the channel region 62 and the conductors 58a and 58b.         3. The interface between the conductors 58a and 58b, and the substrate 50, specifically near the channel region 62, should preferably be angled relative to the channel, as opposed to coplanar relative to the channel, to reduce the mean path length required for carriers to travel between the interface and the channel.        
If the implantation, or other means, of forming the source/drain regions 54 and 56 is omitted without constraining the length of spacer 60 on at least the source side, and perhaps also the drain side, the device resistance will be excessive due to the need for the current to flow through a region of relatively low electron (n-channel FET) or hole (p-channel FET) concentration. With the implant, the spacer length is substantially less constrained, as the source/drain region generally has relatively high conductivity, and thus resistance between the edge of the channel and the source/drain contacts 58a and 58b is relatively small. The key difference is that with damascene contacts to a source/drain, the electrons (n-channel FET) or holes (p-channel FET) for the channel are provided by a source other than the damascene conductor, e.g., an n+-implanted region in the example of the '356 patent. This requires near proximity of the source to the channel, and of the contact to the source, but not of the contact to the channel.
Hiruta offers no suggestion as to how or even if the processes described in the '356 patent could be extended to an actual damascene source/drain. For example, the process discussed in the '356 patent includes no etch of the semiconductor in the source/drain region, and therefore fails to account for source-to-gate overlap. This is perhaps not surprising as, to date, silicon device technologies designed for low transistor resistance in the “on” state have been designed with source-to-gate overlap (see, e.g., the '356 patent). This is also true with metal source/drains (see, e.g., the '103 patent cited above). The present inventors have, however, shown that for short-channel transistors with a low Schottky barrier, overlap of the source and gate is detrimental to switching speed. See D. Connelly et al., Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance, IEEE Electron Device Letters, v.24, n.6, pp. 411-413 (2003).
In addition to the above concern, the '356 patent places no limitation on the length of the gate spacers, a critical parameter for the optimization of deposited source/drain MOSFETs without source-to-gate overlap. Nor does the '356 patent offer guidance for extending the gate electrode over the field region. Because gates are typically designed with length-axis dimensions nearly as short as can be reliably defined in a technology, aligning a contact to the gate over the channel is impractical without locally lengthening the channel, which would yield a large capacitance penalty. Instead, the gate electrode is typically extended over the field, a region where the per-area capacitance is reduced, for example due to the presence of a thick insulator, for contact to one or more subsequent metal layers.
For at least these reasons then, the process described in the '356 patent is not suitable for forming self-aligned, deposited source/drain, insulated gate FETs, and so an alternative procedure is needed.